1. Field of the Invention
The present invention relates generally to methods for fabricating spacer layers within microelectronic fabrications. More particularly, the present invention relates to methods for fabricating, with enhanced dimensional control, spacer layers within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly more common in the art of microelectronic fabrication to form adjoining sidewalls of patterned microelectronic conductor layers within microelectronic fabrications microelectronic spacer layers formed of dielectric materials. Microelectronic spacer layers are desirable in the art of microelectronic fabrication formed adjoining sidewalls of patterned microelectronic conductor layers within microelectronic fabrications insofar as microelectronic spacer layers assist in: (1) providing for adequate separation of adjoining or adjacent microelectronic conductor layers and microelectronic conductor regions within microelectronic fabrications (such as when microelectronic spacer layers are formed adjoining sidewalls of gate electrode microelectronic conductor layers within field effect transistor (FET) devices within semiconductor integrated circuit microelectronic fabrications to separate the same from source/drain microelectronic conductor regions within field effect transistor (FET) devices formed within the semiconductor integrated circuit microelectronic fabrications); or (2) providing for reduced defects, such as void defects, when forming dielectric layers interposed between patterned microelectronic conductor layers within microelectronic fabrications, including but not limited to semiconductor integrated circuit microelectronic fabrications.
While microelectronic spacer layers are thus desirable in the art of microelectronic fabrication and often essential in the art of microelectronic fabrication, microelectronic spacer layers are nonetheless not entirely without problems in the art of microelectronic fabrication.
In that regard, it is often difficult in the art of microelectronic fabrication to fabricate within microelectronic fabrications microelectronic spacer layers with enhanced dimensional control.
It is thus desirable in the art of microelectronic fabrication to fabricate within microelectronic fabrications microelectronic spacer layers with enhanced dimensional control.
It is towards the foregoing object that the present invention is directed.
Various microelectronic spacer layers having desirable properties, and methods for fabrication thereof, have been disclosed in the art of microelectronic fabrication.
Included among the microelectronic spacer layers and methods for fabrication thereof, but not limiting among the microelectronic spacer layers and methods for fabrication thereof, are microelectronic spacer layers and methods for fabrication thereof disclosed within: (1) Chen et al., in U.S. Pat. No. 5,573,965 (a multi-step conformal microelectronic dielectric spacer material layer formation method which provides, upon anisotropic etching of a series of conformal dielectric spacer material layers formed employing the method, a microelectronic dielectric spacer layer with enhanced dimensional control); (2) Gardner et al., in U.S. Pat. No. 5,899,721 (a multi-step microelectronic dielectric spacer layer fabrication method which provides horizontally laminated microelectronic dielectric spacer layers with diminished linewidth); (3) Hause et al., in U.S. Pat. No. 6,051,863 (a microelectronic dielectric spacer layer, and method for fabrication thereof, having a reentrant cross-sectional profile to provide for enhanced isolation of field effect transistor (FET) device gate electrode and source/drain region structures separated by the microelectronic dielectric spacer layer); and (4) Lam et al., in U.S. Pat. No. 6,190,961 (a two-step multiple step etch method for forming within a microelectronic fabrication a microelectronic spacer layer with a square shape having enhanced isolation properties).
The disclosures of each of the foregoing references are incorporated herein fully by reference.
Desirable in the art of microelectronic fabrication are additional methods for fabricating within microelectronic fabrications microelectronic spacer layers with enhanced dimensional control.
It is towards the foregoing object that the present invention is directed.
A first object of the present invention is to provide a method for fabricating a spacer layer within a microelectronic fabrication.
A second object of the present invention is to provide a method in accord with the first object of the present invention, wherein the spacer layer is fabricated with enhanced dimensional control.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a spacer layer within a microelectronic fabrication.
To practice the method of the present invention, there is first provided a substrate having formed thereover a topographic feature. There is then formed over the substrate including the topographic feature a first layer of a first material having formed thereupon a second layer of a second material. There is then etched, while employing a first etch method having a first enhanced etch selectivity for the second material with respect to the first material, the second layer to form therefrom a second spacer layer formed upon the first layer. There is then etched, while employing a second etch method having a second substantially neutral etch selectivity for the second material with respect to the first material, the second spacer layer and first layer to form therefrom an etched second spacer layer formed upon a partially etched first layer. Finally, there is then etched, while employing a third etch method having a third enhanced etch selectivity for the first material with respect to the second material, the partially etched first layer to form a first spacer layer having formed thereupon the etched second spacer layer.
The present invention provides a method for fabricating a spacer layer within a microelectronic fabrication, wherein the spacer layer is fabricated with enhanced dimensional control.
The present invention realizes the foregoing object by employing when fabricating a spacer layer within a microelectronic fabrication a three step multi-step etch method for forming the spacer layer within the microelectronic fabrication from a second layer formed of a second material laminated to a first layer formed of a first material in turn formed over a topographic feature further in turn formed over a substrate employed within the microelectronic fabrication. Within the three step multi-step etch method there is employed sequentially: (1) a first etch method having a first enhanced etch selectivity for the second material with respect to the first material; (2) a second etch method having a second substantially neutral etch selectivity for the second material with respect to the first material; and (3) a third etch method having a third enhanced etch selectivity for the first material with respect to the second material.